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i960 ? vh embedded-pci processor preliminary datasheet product features n high performance 80960jt core sustained one instruction/clock execution 16 kbyte two-way set-associative instruction cache 4 kbyte direct-mapped data cache sixteen 32-bit global registers sixteen 32-bit local registers programmable bus widths: 8-, 16-, 32-bit 1 kbyte internal data ram local register cache (eight available stack frames) two 32-bit on-chip timer units core clock rate: 1x, 2x or 3x local bus clock n pci interface complies with pci local bus specification 2.2 runs at local bus clock rate 5 volts pci signaling environment n address translation unit connects local bus to pci bus inbound/outbound address translation support direct outbound addressing support n messaging unit four message registers two doorbell registers n memory controller 256 mbytes of 32- or 36-bit dram interleaved or non-interleaved dram fast page-mode dram support extended data out dram support two independent banks for sram / rom / flash (16 mbytes/bank; 8- or 32-bit) n dma controller two independent channels pci memory controller interface 32-bit local bus addressing 64-bit pci bus addressing independent interface to pci bus 132 mbyte/sec burst transfers to pci and local buses direct addressing to and from pci buses unaligned transfers supported in hardware channels dedicated to pci bus n i 2 c bus interface unit serial bus master/slave capabilities system management functions n 3.3 v supply 5 v tolerant inputs ttl compatible outputs n plastic bga* package 324 ball-grid array (pbga) order number: 273179-004 april 1999 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
preliminary datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the i960 ? vh processor may contain design defects or errors known as errata which may cause the product to deviate from published specif ications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1999 *third-party brands and names are the property of their respective owners.
preliminary datasheet 3 80960vh contents 1.0 about this document......................................................................................................... 7 1.1 solutions960 ? program.........................................................................................7 1.2 terminology...........................................................................................................7 1.3 additional information sources .............................................................................7 2.0 functional overview......................................................................................................... ..8 2.1 key functional units ............................................................................................. 9 2.1.1 dma controller.........................................................................................9 2.1.2 address translation unit ..........................................................................9 2.1.3 messaging unit.........................................................................................9 2.1.4 memory controller....................................................................................9 2.1.5 core and peripheral unit.......................................................................... 9 2.1.6 i2c bus interface unit ..............................................................................9 2.2 i960 ? core features (80960jt) .......................................................................... 10 2.2.1 burst bus................................................................................................11 2.2.2 timer unit...............................................................................................11 2.2.3 priority interrupt controller .....................................................................11 2.2.4 faults and debugging ............................................................................ 11 2.2.5 on-chip cache and data ram .............................................................. 12 2.2.6 local register cache .............................................................................12 2.2.7 test features .........................................................................................12 2.2.8 memory-mapped control registers ....................................................... 12 2.2.9 instructions, data types and memory addressing modes .....................13 3.0 package information ........................................................................................................1 5 3.1 package introduction........................................................................................... 15 3.1.1 functional signal definitions ..................................................................15 3.1.2 324-lead pbga package ...................................................................... 25 3.2 package thermal specifications .........................................................................33 3.2.1 thermal specifications ...........................................................................33 3.2.1.1 ambient temperature................................................................33 3.2.1.2 case temperature ....................................................................33 3.2.1.3 thermal resistance ..................................................................34 3.2.2 thermal analysis....................................................................................34 4.0 electrical specifications................................................................................................... .35 4.1 v cc5 pin requirements (v diff ) ..........................................................................35 4.2 v ccpll pin requirements ................................................................................... 36 4.3 dc specifications ................................................................................................37 4.4 ac specifications ................................................................................................39 4.4.1 relative output timings .........................................................................41 4.4.2 memory controller relative output timings ..........................................41 4.4.3 boundary scan test signal timings ...................................................... 43 4.4.4 i2c interface signal timings ..................................................................44 4.5 ac test conditions ............................................................................................. 44 4.6 ac timing waveforms ........................................................................................45 4.7 memory controller output timing waveforms ....................................................48
80960vh 4 preliminary datasheet 5.0 bus functional waveforms ..............................................................................................54 6.0 device identification on reset ......................................................................................... 63 figures 1 product name functional block diagram ............................................................. 8 2 80960jt core block diagram ............................................................................. 10 3 324-plastic ball grid array top and side view ................................................... 25 4 324-plastic ball grid array (top view)................................................................ 26 5 thermocouple attachment .................................................................................. 33 6v cc5 current-limiting resistor ...........................................................................36 7v ccpll lowpass filter ........................................................................................ 36 8 ac test load ...................................................................................................... 44 9 p_clk, tclk waveform .................................................................................... 45 10 t ov output delay waveform .............................................................................. 45 11 t of output float waveform................................................................................ 46 12 t is and t ih input setup and hold waveform ...................................................... 46 13 t lxl and t lxa relative timings waveform ........................................................46 14 dt/r# and den# timings waveform ................................................................. 47 15 i 2 c interface signal timings................................................................................ 47 16 fast page-mode read access, non-interleaved, 2,1,1,1 wait state, 32-bit 80960 local bus ............................................................................................................48 17 fast page-mode write access, non-interleaved, 2,1,1,1 wait states, 32-bit 80960 local bus ............................................................................................................49 18 fpm dram system read access, interleaved, 2,0,0,0 wait states.................. 50 19 fpm dram system write access, interleaved, 1,0,0,0 wait states ..................51 20 edo dram, read cycle .................................................................................... 52 21 edo dram, write cycle .................................................................................... 52 22 32-bit bus, sram read accesses with 0 wait states ....................................... 53 23 32-bit bus, sram write accesses with 0 wait states........................................ 53 24 non-burst read and write transactions without wait states, 32-bit 80960 local bus ...................................................................................................................... 54 25 burst read and write transactions without wait states, 32-bit 80960 local bus ............................................................................................................55 26 burst write transactions with 2,1,1,1 wait states, 32-bit 80960 local bus ....... 56 27 burst read and write transactions without wait states, 8-bit 80960 local bus57 28 burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit 80960 local bus ............................................................................ 58 29 bus transactions generated by double word read bus request, misaligned one byte from quad word boundary, 32-bit 80960 local bus................................. 59 30 hold/holda waveform for bus arbitration .................................................... 60 31 80960 core cold reset waveform ..................................................................... 61 32 80960 local bus warm reset waveform ........................................................... 62
preliminary datasheet 5 80960vh tables 1 related documentation.........................................................................................7 2 80960vh instruction set .....................................................................................14 3 signal type definition ......................................................................................... 15 4 signal descriptions.............................................................................................. 16 5 power requirement, processor control and test signal descriptions ............... 19 6 interrupt unit signal descriptions........................................................................20 7 pci signal descriptions....................................................................................... 21 8 memory controller signal descriptions ............................................................... 22 9dma, i 2 c units signal descriptions .................................................................... 24 10 clock related signals ......................................................................................... 24 11 pbga 324 package dimensions.........................................................................26 12 324-plastic ball grid array ballout in ball order ............................................ 27 13 324-plastic ball grid array ballout in signal order ........................................30 14 324-lead pbga package thermal characteristics ............................................ 34 15 absolute maximum ratings.................................................................................35 16 operating conditions...........................................................................................35 17 v diff specification for dual power supply requirements (3.3 v, 5 v) ............... 36 18 dc characteristics ..............................................................................................37 19 i cc characteristics ..............................................................................................38 20 input clock timings............................................................................................. 39 21 synchronous output timings ..............................................................................39 22 synchronous input timings................................................................................. 40 23 relative output timings ......................................................................................41 24 fast page mode non-interleaved dram output timings...................................41 25 fast page mode interleaved dram output timings ..........................................41 26 edo dram output timings................................................................................42 27 sram/rom output timings ...............................................................................42 28 boundary scan test signal timings ................................................................... 43 29 i2c interface signal timings ............................................................................... 44 30 processor device id register - pdidr..............................................................63

80960vh preliminary datasheet 7 1.0 about this document this is the preliminary data sheet for the low-power (3.3 v) version of intels i960 ? vh processor (80960vh) family. this data sheet contains a functional overview, mechanical data (package signal locations and simulated thermal characteristics), targeted electrical specifications (simulated), and bus functional waveforms. detailed functional descriptions other than parametric performance is published in the i960 ? vh processor developers manual. 1.1 solutions960 ? program intels solutions960 ? program features a wide variety of development tools which support the i960 processor family. many of these tools are developed by partner companies; some are developed by intel, such as profile-driven optimizing compilers. for more information on these products, contact your local intel representative. 1.2 terminology in this document, the following terms are used: ? local bus refers to the 80960vhs internal local bus, not the pci local bus. ? primary pci bus is the 80960vhs internal pci bus which conforms to pci sig specifications. ? 80960 core refers to the 80960jt processor which is integrated into the 80960vh. 1.3 additional information sources intel documentation is available from your local intel sales representative or intel literature sales. call 1-800-879-4683 or visit intel's website at http://www.intel.com. table 1. related documentation document title order / contact i960 ? vh processor developers manual intel order # 273173 i960? jx microprocessor users guide intel order # 272483 pci local bus specification , revision 2.2 pci special interest group 1-800-433-5177 i 2 c peripherals for microcontrollers philips semiconductor
80960vh 8 preliminary datasheet 2.0 functional overview as indicated in figure 1 , the 80960vh combines many features with the 80960jt to create a highly integrated processor. subsections following the figure briefly describe the main features; for detailed functional descriptions, refer to the i960 ? vh processor developers manual. the pci bus is an industry standard, high performance, low latency system bus that operates up to 132 mbyte/sec. the 80960vh is fully compliant with the pci local bus specification , revision 2.2. function 0 is the address translation unit. the 80960vh, object code compatible with the i960 core processor, is capable of sustained execution at the rate of one instruction per clock. the local bus, a 32-bit multiplexed burst bus, is a high-speed interface to system memory and i/o. a full complement of control signals simplifies the connection of the 80960vh to external components. physical and logical memory attributes are programmed via memory-mapped control registers (mmrs), an extension not found on the i960 kx, sx or cx processors. physical and logical configuration registers enable the processor to operate with all combinations of bus width and data object alignment. figure 1. product name functional block diagram i 960 ? jt core processor primary pci bus local memory i 2 c bus interface unit memory controller internal arbitration i 2 c serial bus address translation unit two dma channels core and peripheral control unit local bus primary atu messaging unit
80960vh preliminary datasheet 9 2.1 key functional units 2.1.1 dma controller the dma controller supports low-latency, high-throughput data transfers between pci bus agents and 80960 local memory. two separate dma channels accommodate data transfers for the primary pci bus. the dma controller supports chaining and unaligned data transfers. it is programmable only through the i960 core processor. 2.1.2 address translation unit the address translation unit (atu) allows pci transactions direct access to the 80960vh local memory. the 80960vh has direct access to the pci bus. the atu supports transactions between pci address space and 80960vh address space. address translation is controlled through programmable registers accessible from the pci interface and the 80960 core. dual access to registers allows flexibility in mapping the two address spaces. 2.1.3 messaging unit the messaging unit (mu) provides data transfer between the pci system and the 80960vh. it uses interrupts to notify each system when new data arrives. the mu has two messaging mechanisms. each allows a host processor or external pci device and the 80960vh to communicate through message passing and interrupt generation. the two mechanisms are message registers and doorbell registers. 2.1.4 memory controller the memory controller allows direct control of external memory systems, including dram, sram, rom and flash memory. it provides a direct connect interface to memory that typically does not require external logic. it features programmable chip selects, a wait state generator and byte parity. external memory can be configured as pci addressable memory. 2.1.5 core and peripheral unit the core and peripheral unit allows software to control the 80960vh through the primary pci bus. for example, the 80960 processor core and the 80960vh local bus can be reset via the pci bus. 2.1.6 i 2 c bus interface unit the i 2 c (inter-integrated circuit) bus interface unit allows the 80960 core to serve as a master and slave device residing on the i 2 c bus. the i 2 c bus is a serial bus developed by philips semiconductor consisting of a two pin interface. the bus allows the 80960vh to interface to other i 2 c peripherals and microcontrollers for system management functions. it requires a minimum of hardware for an economical system to relay status and reliability information on the i/o subsystem to an external device. for more information, see i 2 c peripherals for microcontrollers (philips semiconductor).
80960vh 10 preliminary datasheet 2.2 i960 ? core features (80960jt) the processing power of the 80960vh comes from the 80960jt processor core. the 80960jt is a new, scalar implementation of the 80960 core architecture. figure ? shows a block diagram of the 80960jt core processor. factors that contribute to the 80960 family cores performance include: ? single-clock execution of most instructions ? independent multiply/divide unit ? efficient instruction pipeline minimizes pipeline break latency ? register and resource scoreboarding allow overlapped instruction execution ? 128-bit register bus speeds local register caching ? 16 kbyte two-way set-associative, integrated instruction cache ? 4 kbyte direct-mapped, integrated data cache ? 1 kbyte integrated data ram delivers zero wait state program data the 80960 core operates out of its own 32-bit address space, which is independent of the pci address space. the local bus memory can be: ? made visible to the pci address space ? kept private to the 80960 core ? allocated as a combination of the two figure 2. 80960jt core block diagram programmable bus control unit interrupt controller control address/ instruction sequencer physical region configuration interrupt port 1k byte data ram memory interface execution multiply unit divide unit memory-mapped register interface data bus global / local register file src2 dst src1 address control effective constants generation unit address 32-bit addr 32-bit data bus request queues and two 32-bit timers 8-set local register src1 src2 dst pll, clocks, power mgmt boundary scan controller ta p 5 128 src1 src2 dst src1 dst 9 32 32-bit buses address / data 3 independent 32-bit src1, src2, and dst buses instruction cache 16 kbyte two-way set 4kbyte direct mapped data cache p_clk cache
80960vh preliminary datasheet 11 2.2.1 burst bus a 32-bit high-performance bus controller interfaces the 80960vh to external memory and peripherals. the bus control unit fetches instructions and transfers data on the local bus at the rate of up to four 32-bit words per six clock cycles. the external address/data bus is multiplexed. users may configure the 80960vhs bus controller to match an applications fundamental memory organization. physical bus width is programmable for up to eight regions. data caching is programmed through a group of logical memory templates and a defaults register. the bus control units features include: ? multiplexed external bus minimizes pin count ? 32-, 16- and 8-bit bus widths simplify i/o interfaces ? external ready control for address-to-data, data-to-data and data-to-next-address wait state types ? little endian byte ordering ? unaligned bus accesses performed transparently ? three-deep load/store queue decouples the bus from the 80960 core upon reset, the 80960vh conducts an internal self test. before executing its first instruction, it performs an external bus confidence test by performing a checksum on the first words of the initialization boot record. 2.2.2 timer unit the timer unit (tu) contains two independent 32-bit timers that are capable of counting at several clock rates and generating interrupts. each is programmed by use of the timer unit registers. these memory-mapped registers are addressable on 32-bit boundaries. the timers have a single- shot mode and auto-reload capabilities for continuous operation. each timer has an independent interrupt request to the 80960vhs interrupt controller. the tu can generate a fault when unauthorized writes from user mode are detected. 2.2.3 priority interrupt controller low interrupt latency is critical to many embedded applications. as part of its highly flexible interrupt mechanism, the 80960vh exploits several techniques to minimize latency: ? interrupt vectors and interrupt handler routines can be reserved on-chip ? register frames for high-priority interrupt handlers can be cached on-chip ? the interrupt stack can be placed in cacheable memory space 2.2.4 faults and debugging the 80960vh employs a comprehensive fault model. the processor responds to faults by making implicit calls to a fault handling routine. specific information collected for each fault allows the fault handler to diagnose exceptions and recover appropriately.
80960vh 12 preliminary datasheet the processor also has built-in debug capabilities. via software, the 80960vh may be configured to detect as many as seven different trace event types. alternatively, mark and fmark instructions can generate trace events explicitly in the instruction stream. hardware breakpoint registers are also available to trap on execution and data addresses. 2.2.5 on-chip cache and data ram external memory subsystems often impose substantial wait state penalties. the 80960vh integrates considerable storage resources on-chip to decouple cpu execution from the external bus by including a 16 kbyte instruction cache, a 4 kbyte data cache and 1 kbyte data ram. 2.2.6 local register cache the 80960vh rapidly allocates and deallocates local register sets during context switches. the processor needs to flush a register set to the stack only when it saves more than seven sets to its local register cache. 2.2.7 test features the 80960vh incorporates numerous features that enhance the users ability to test both the processor and the system to which it is attached. these features include once (on-circuit emulation) mode and boundary scan (jtag). the 80960vh provides testability features compatible with ieee standard test access port and boundary scan architecture (ieee std. 1149.1). one of the boundary scan instructions, highz, forces the processor to float all its output pins (once mode). once mode can also be initiated at reset without using the boundary scan mechanism. once mode is useful for board-level testing. this feature allows a mounted 80960vh to electrically remove itself from a circuit board. this mode allows system-level testing where a remote tester can exercise the processor system. the test logic does not interfere with component or system behavior and ensures that components function correctly, and also the connections between various components are correct. the jtag boundary scan feature is an alternative to conventional bed-of-nails testing. it can examine connections that might otherwise be inaccessible to a test system. 2.2.8 memory-mapped control registers the 80960vh is compliant with 80960 family architecture and has the added advantage of memory-mapped, internal control registers not found on the 80960kx, sx or cx processors. this feature provides software an interface to easily read and modify internal control registers. each memory-mapped, 32-bit register is accessed via regular memory-format instructions. the processor ensures that these accesses do not generate external bus cycles.
80960vh preliminary datasheet 13 2.2.9 instructions, data types and memory addressing modes as with all 80960 family processors, the 80960vh instruction set supports several different data types and formats: ? bit ? bit fields ? integer (8-, 16-, 32-, 64-bit) ? ordinal (8-, 16-, 32-, 64-bit unsigned integers) ? triple word (96 bits) ? quad word (128 bits) the 80960vh provides a full set of addressing modes for c and assembly: ? two absolute modes ? five register indirect modes ? index with displacement mode ? ip with displacement mode table 2 shows the available instructions.
80960vh 14 preliminary datasheet table 2. 80960vh instruction set data movement arithmetic logical bit, bit field and byte load store move conditional select load address add subtract multiply divide remainder modulo shift extended shift extended multiply extended divide add with carry subtract with carry conditional add conditional subtract rotate and not and and not or exclusive or not or or not nor exclusive nor not nand set bit clear bit not bit alter bit scan for bit span over bit extract modify scan byte for equal byte swap comparison branch call/return fault compare conditional compare compare and increment compare and decrement test condition code check bit unconditional branch conditional branch compare and branch call call extended call system return branch and link conditional fault synchronize faults debug processor management atomic modify trace controls mark force mark flush local registers modify arithmetic controls modify process controls halt system control cache control interrupt control atomic add atomic modify
80960vh preliminary datasheet 15 3.0 package information 3.1 package introduction the 80960vh is offered in a plastic ball grid array (pbga) package. this is a perimeter array package with five rows of ball connections in the outer area of the package. see figure , (pg. 26) . section 3.1.1, functional signal definitions describes signal function. section 3.1.2, 324-lead pbga package defines the signal and ball locations. 3.1.1 functional signal definitions table 3 presents the legend for interpreting the type field in the following tables. table 4 defines signals associated with the bus interface. table 5 defines signals associated with basic control and test functions. table 6 defines signals associated with the interrupt unit. table 7 defines pci signals. table 8 defines memory controller signals. table 9 defines dma, and i 2 c signals. table 10 defines clock signals. table 3. signal type definition symbol description i input signal only. o output signal only. i/o signal can be either an input or output. od open drain signal. C signal must be connected as described. s (...) synchronous. inputs must meet setup and hold times relative to p_clk. s(e) edge sensitive input s(l) level sensitive input a (...) asynchronous. inputs may be asynchronous relative to p_clk. a(e) edge sensitive input a(l) level sensitive input r (...) while the p_rst# signal is asserted, the signal: r(1) is driven to v cc r(0) is driven to v ss r(q) is a valid output r(z) floats r(h) is pulled up to v cc r(x) is driven to an unknown state
80960vh 16 preliminary datasheet h (...) while the is in the hold state, the signal: h(1) is driven to v cc h(0) is driven to v ss h(q) maintains previous state or continues to be a valid output h(z) floats p (...) while the 80960vh is halted, the signal: p(1) is driven to v cc p(0) is driven to v ss p(q) maintains previous state or continues to be a valid output k (...) while the pci bus is in park mode, the pin: k(z) floats k(q) maintains previous state or continues to be a valid output table 4. signal descriptions (sheet 1 of 4) name type description ad31:0 i/o s(l) r(z) h(z) p(q) address / data bus carries 32-bit physical addresses and 8-, 16- or 32- bit data to and from memory. during an address ( t a ) cycle, bits 2-31 contain a physical word address (bits 0-1 indicate size; see below). during a data (t d ) cycle, read or write data is present on one or more contiguous bytes, comprising ad31:24, ad23:16, ad15:8 and ad7:0. during write operations, unused signals are driven to determinate values. size , which comprises bits 0-1 of the ad lines during a t a cycle, specifies the number of data transfers during the bus transaction on the local bus. when the dma or atus initiate data transfers, transfer size shown below is not valid. ad1 ad0 bus transfers 0 0 1 transfer 0 1 2 transfers 1 0 3 transfers 1 1 4 transfers when the 80960vh enters halt mode and the previous bus operation was: ? write ad31:2 are driven with the last data value on the ad bus. ? read ad31:2 are driven with the last address value on the ad bus. typically, ad1:0 reflect the size information of the last bus transaction (either instruction fetch or load/store) that was executed before entering halt mode. ads# o r(1) h(z) p(1) address strobe indicates a valid address and the start of a new bus access. the processor asserts ads# for the entire t a cycle. external bus control logic typically samples ads# at the end of the cycle. ale o r(0) h(z) p(0) address latch enable indicates the transfer of a physical address. ale is asserted during a t a cycle and deasserted before the beginning of the t d state. it is active high and floats to a high impedance state during a hold cycle (t h ). blast# o r(h) h(z) p(1) burst last indicates the last transfer in a bus access. blast# is asserted in the last data transfer of burst and non-burst accesses. blast# remains active while wait states are detected via the lrdyrcv# or rdyrcv# signal on the memory controller. blast# becomes inactive after the final data transfer in a bus cycle. blast# has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = last data transfer 1 = not the last data transfer table 3. signal type definition symbol description
80960vh preliminary datasheet 17 be3:0# o r(1) h(z) p(1) byte enables select which of up to four data bytes on the bus participate in the current bus access. byte enable encoding depends on the bus width of the memory region accessed: 32-bit bus: be3# enables data on ad31:24 be2# enables data on ad23:16 be1# enables data on ad15:8 be0# enables data on ad7:0 16-bit bus: be3# becomes byte high enable (enables data on ad15:8) be2# is not used (state is high) be1# becomes address bit 1 (a1) (increments with the assertion of lrdy# or rdyrcv#) be0# becomes byte low enable (enables data on ad7:0) 8-bit bus: be3# is not used (state is high) be2# is not used (state is high) be1# becomes address bit 1 (a1) (increments with the assertion of lrdy# or rdyrcv#) be0# becomes address bit 0 (a0) (increments with the assertion of lrdy# or rdyrcv#) the processor asserts byte enables, byte high enable and byte low enable during t a . since unaligned bus requests are split into separate bus transactions, these signals do not toggle during a burst (32-bit bus only) from the i960 core processor; they do toggle for dma and atu cycles. they remain active through the last t d cycle. den# o r(h) h(z) p(1) data enable indicates data transfer cycles during a bus access. den# is asserted at the start of the first data cycle in a bus access and deasserted at the end of the last data cycle. den# is used with dt/r# to provide control for data transceivers connected to the data bus. den# has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = data cycle 1 = not a data cycle d/c# / rst_mode# i/o r(h) h(z) p(q) data/code/reset_mode indicates that a bus access is a data access or an instruction access. d/c# has the same timing as w/r#. 0 = instruction access 1 = data access the rst_mode# signal is sampled at primary pci bus reset to determine whether the 80960 core is to be held in reset. when rst_mode# is high, the 80960vh begins initialization immediately following the deassertion of p_rst#. when rst_mode# is low, the 80960 core remains in reset until the 80960 core reset bit is cleared in the reset/retry control register. this signal has a weak internal pullup that is active during reset to ensure normal operation when the signal is left unconnected. 0 = rst_mode enabled 1 = rst_mode not enabled while the 80960 core is in reset, all peripherals may be accessed from the primary pci bus depending on the status of the width/hltd1/retry/ signal. dt/r# o r(0) h(z) p(q) data transmit/receive indicates the direction of data transfer to and from the address/data bus. it is low during t a and t w /t d cycles for a read; it is high during t a and t w /t d cycles for a write. dt/r# never changes state when den# is asserted. 0 = receive 1 = transmit table 4. signal descriptions (sheet 2 of 4) name type description
80960vh 18 preliminary datasheet lock#/once# i/o s(l) r(h) h(z) p(q) bus lock indicates that an atomic read-modify-write operation is in progress. the lock# output is asserted in the first clock of an atomic operation and deasserted in the last data transfer of the sequence. the processor does not grant holda while asserting lock#. this prevents external agents from accessing memory involved in semaphore operations. 0 = atomic read-modify-write in progress 1 = no atomic read-modify-write in progress once mode: the processor samples the once input during reset. when once# is asserted low at the end of reset, the processor enters once mode, stops all clocks and floats all output signals. this signal has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. 0 = once mode enabled 1 = once mode not enabled lrdyrcv#/ stest i/o r(h) h(q) p(q) local ready/recover , generated by the 80960vh s memory controller unit, is an output version of the ready/recover (rdyrcv#) signal. refer to the rdyrcv# signal description. self test enables or disables the processors internal self-test feature at initialization. stest is examined at the end of p_rst#. when stest is asserted, the processor performs its internal self-test and the external bus confidence test. when stest is deasserted, the processor performs only the external bus confidence test. this signal has a weak internal pullup which is active during reset to ensure normal operation. 0 = self test disabled 1 = self test enabled hold i s(l) hold is a request from an external bus master to acquire the bus. when the processor receives hold and grants bus control to another master, it asserts holda, floats the address/data and control lines and enters the t h state. when hold is deasserted, the processor deasserts holda and enters either the t i or t a state, resuming control of the address/data and control lines. see figure , (pg. 61) . 0 = no hold request 1 = hold requested holda o r(0) h(1) p(q) hold acknowledge indicates to an external bus master that the processor has relinquished bus control. the processor can grant hold requests and enter the t h state and while halted as well as during regular operation. see figure , (pg. 61) . 0 = no hold acknowledged 1 = hold acknowledged rdyrcv# i s(l) ready/recover is only used in systems that use an external memory controller (and do not use the 80960vhs memory controller unit). this signal indicates that data on ad lines can be sampled or removed. when rdyrcv# is not asserted during a t d cycle, the t d cycle extends to the next cycle by inserting a wait state (t w ). 0 = sample data 1 = do not sample data rdyrcv# has an alternate function during the recovery (t r ) state. the processor continues to insert recovery states until it samples the signal high. this gives slow external devices more time to float their buffers before the processor drives addresses. 0 = insert wait states 1 = recovery complete when using the internal memory controller, connect this signal to v cc through a 2.7 k w resistor. table 4. signal descriptions (sheet 3 of 4) name type description
80960vh preliminary datasheet 19 w/r# o r(0) h(z) p(q) write/read specifies during a t a cycle whether the operation is a write or read. it is latched on-chip and remains valid during t d cycles. 0 = read 1 = write width/ hltd0 i/o r(h) h(z) p(q) width denotes the physical memory attributes for a bus transaction in conjunction with width/hltd1/retry: width/hltd1/retry width/hltd0 0 0 8 bits wide 0 1 16 bits wide 1032 bits wide 11 undefined width/hltd0 for proper operation, do not connect this signal to ground. this signal has a weak internal pullup which is active during reset to ensure normal operation. hltd0 signal name has no function in the 80960vh; the signal name is included for 80960jt naming convention compatibility. width/ hltd1/ retry i/o r(h) h(z) p(q) width denotes the physical memory attributes for a bus transaction in conjunction with the width/hltd0 signal. refer to description above. retry is sampled at primary pci bus reset to determine when the primary pci interface is disabled. when high, the primary pci interface disables pci configuration cycles by signaling a retry until the reset/retry control registers configuration cycle disable bit is cleared. when low, the primary pci interface allows configuration cycles to occur. width/hltd1/retry has a weak internal pullup which is active during reset to ensure normal operation when the signal is not connected. when the rst_mode# pin is asserted, retry is internally forced low [inactive] regardless of its external state. hltd1 signal name has no function in the 80960vh; the signal name is included for 80960jt naming convention compatibility. table 5. power requirement, processor control and test signal descriptions (sheet 1 of 2) name type description fail# o r(0) h(q) fail indicates a failure of the processors built-in self-test performed during initialization. fail# is asserted immediately upon reset and toggles during self-test to indicate the status of individual tests: ? when self-test passes, the processor deasserts fail# and commences operation from user code. ? when self-test fails, the processor asserts fail# and then stops executing. 0 = self test failed 1 = self test passed l_rst# o local bus reset notifies external devices that the local bus has reset. tck i test clock is a cpu input that provides the clocking function for ieee 1149.1 boundary scan testing (jtag). state information and data are clocked into the processor on the rising edge; data is clocked out of the processor on the falling edge. tdi i s(l) test data input is the serial input signal for jtag. tdi is sampled on the rising edge of tck, during the shift-ir and shift-dr states of the test access port. this signal has a weak internal pullup to ensure normal operation. table 4. signal descriptions (sheet 4 of 4) name type description
80960vh 20 preliminary datasheet tdo o r(q) h(q) p(q) test data output is the serial output signal for jtag. tdo is driven on the falling edge of tck during the shift-ir and shift-dr states of the test access port. at other times, tdo floats. tms i s(l) test mode select is sampled at the rising edge of tck to select the operation of the test logic for ieee 1149.1 boundary scan testing. this signal has a weak internal pullup to ensure normal operation. trst# i a(l) test reset asynchronously resets the test access port (tap) controller function of ieee 1149.1 boundary scan testing (jtag). when using the boundary scan feature, connect a pulldown resistor (1.5 k w ) between this signal and v ss . when tap is not used, this signal must be connected to v ss ; however, no resistor is required. the signal has a weak internal pullup which must be overcome during reset to ensure normal operation. note: the system must ensure that trst# is asserted after power-up to put the tap controller in a known state. failure to do so may cause improper processor operation. lcdinit# i lcd initialization is a static signal used to initialize the internal logic of the lcd960 debugger. this signal has an internal pullup for normal operation. v cc C power . connect to a 3.3 volt power board plane. v cc5 ref C 5 volt reference voltage. input is the reference voltage for the 5 v-tolerant i/o buffers. connect this signal to +5 v for use with signals which exceed 3.3 v. when all inputs are from 3.3 v components, connect this signal to 3.3 v. v ss C ground. connect to a v ss board plane. n.c. C no connect . do not make electrical connections to these balls. vccpll2:1 i pll power . for external connection to a 3.3 v v cc board plane. power to plls requires external filtering. see section 4.2, vccpll pin requirements. table 5. power requirement, processor control and test signal descriptions (sheet 2 of 2) name type description
80960vh preliminary datasheet 21 table 6. interrupt unit signal descriptions name type description nmi# i a(l) non-maskable interrupt causes a non-maskable interrupt event to occur. nmi# is the highest priority interrupt source and is level-detect. when nmi# is unused, it is recommended that you connect it to v cc . xint3:0# i a(l) external interrupt . external devices use this signal to request an interrupt service. these signals operate in dedicated mode, where each signal is assigned a dedicated interrupt level. the xint3:0# signals can be directed as follows: external int. primary pci 80960 core processor xint0# t p_inta# or xint0# xint1# t p_intb# or xint1# xint2# t p_intc# or xint2# xint3# t p_intd# or xint3# xint7:4# i a(l) external interrupt . external devices use this signal to request an interrupt service. these signals operate in dedicated mode, where each signal is assigned a dedicated interrupt level. note: 1. pci signal functions are summarized in this data sheet. refer to the pci local bus specification , revision 2.2 for a more complete definition. table 7. pci signal descriptions (sheet 1 of 2) name type description 1 p_ad31:0 i/o k(q) r(z) primary pci address/data is the primary multiplexed pci address and data bus. p_c/be3:0# i/o k(q) r(z) primary pci bus command and byte enable signals are multiplexed on the same pci signals. during an address phase, p_c/be3:0# define the bus command. during a data phase, p_c/be3:0# are used as byte enables. p_devsel# i/o r(z) primary pci bus device select is driven by a target agent that has successfully decoded the address. as an input, it indicates whether or not an agent has been selected. p_frame# i/o r(z) primary pci bus cycle frame is asserted to indicate the beginning and duration of an access on the primary pci bus. p_gnt# i r(z) primary pci bus grant indicates to the agent that access to the bus has been granted. this is a point-to-point signal. p_idsel i s(l) primary pci bus initialization device select selects the 80960vh during a configuration read or write command on the primary pci bus. p_int[a:d]# o od r(z) primary pci bus interrupt requests an interrupt. the assertion and deassertion of p_intx# is asynchronous to p_clk . a device asserts its p_intx# line when requesting attention from its device driver. once the p_intx# signal is asserted, it remains asserted until the device driver clears the pending request. p_intx# interrupts are level sensitive. p_irdy# i/o r(z) primary pci bus initiator ready indicates the initiating agent's (bus master's) ability to complete the current data phase of the transaction. note: 1. pci signal functions are summarized in this data sheet; refer to the pci local bus specification , revision 2.2 for a more complete definition.
80960vh 22 preliminary datasheet p_lock# i s(l) primary pci bus lock indicates an atomic operation that may require multiple transactions to complete. p_par i/o k(q) r(z) primary pci bus parity . this signal ensures even parity across p_ad31:0 and p_c/be3:0. all pci devices must provide a parity signal. p_perr# i/o r(z) primary pci bus parity error is used for reporting data parity errors during all pci transactions except a special cycle. p_req# o k(q) r(z) primary pci bus request indicates to the arbiter that this agent desires use of the bus. this is a point to point signal. p_rst# i a(l) primary reset brings 80960vh to a consistent state. when p_rst# is asserted: ? pci output signals are driven to a known consistent state. ? pci bus interface output signals are three-stated. ? open drain signals such as p_serr# are floated. ? s_rst# asserts. p_rst# may be asynchronous to p_clk when asserted or deasserted. although asynchronous, deassertion must be guaranteed to be a clean, bounce-free edge. p_serr# i/o od r(z) primary pci bus system error reports address and data parity errors on the special cycle command, or any other system error where the result would be catastrophic. p_stop# i/o r(z) primary pci bus stop indicates that the current target is requesting the master to stop the current transaction on the primary pci bus. p_trdy# i/o r(z) primary pci bus target ready indicates the target agent's (selected device's) ability to complete the current data phase of the transaction. table 7. pci signal descriptions (sheet 2 of 2) name type description 1 note: 1. pci signal functions are summarized in this data sheet; refer to the pci local bus specification , revision 2.2 for a more complete definition.
80960vh preliminary datasheet 23 table 8. memory controller signal descriptions (sheet 1 of 2) name type description cas7:0# o r(1) h(q) p(q) column address strobe signals are used for dram accesses and are asserted when the ma11:0 signals contain a valid column address. cas7:0# signals are asserted during refresh. non-interleaved operation: cas0#,cas4# = be0# lane access cas1#,cas5# = be1# lane access cas2#,cas6# = be2# lane access cas3#,cas7# = be3# lane access interleaved operation: cas0# = be0# even leaf lane access cas1# = be1# even leaf lane access cas2# = be2# even leaf lane access cas3# = be3# even leaf lane access cas4# = be0# odd leaf lane access cas5# = be1# odd leaf lane access cas6# = be2# odd leaf lane access cas7# = be3# odd leaf lane access ce1:0# o r(1) h(q) p(q) chip enable signals indicate an access to one of the two sram/ flash/ rom memory banks. ce0# and ce1# are never asserted at the same time. these signals are valid during the entire memory operation. ce0# is asserted for accesses to memory bank 0. ce1# is asserted for accesses to memory bank 1. dale1:0 o r(0) h(q) p(q) dram address latch enable signals support external address demultiplexing of the ma11:0 address lines for interleaved dram systems. use these to directly interface to 373 type latches. these signals are only valid for accesses to interleaved memory systems. dale0 is asserted during a valid even leaf address. dale1 is asserted during a valid odd leaf address. dp3:0 i/o r(x) h(q) p(q) data parity carries the parity information for dram accesses. each parity bit corresponds to a group of 8 data bus signals as follows: dp0 ad7:0 dp2 ad23:16 dp1 ad15:8 dp3 ad31:24 the memory controller generates parity information for local bus writes during data cycles. during read data cycles, the memory controller checks parity and provides notification of parity errors on the clock following the data cycle. parity checking and polarity are user-programmable. parity generation and checking are valid only for data lines that have their associated enable bits asserted. dwe1:0# o r(1) h(q) p(q) dram write enable signals distinguish between read and write accesses to dram. dwe1:0# lines are asserted for writes and deasserted for reads. cas7:0# determine valid bytes lanes during the access. these two outputs are functionally equivalent for all dram accesses; these provide increased drive capability for heavily loaded systems. leaf1:0# o r(1) h(q) p(q) leaf enable signals control the data output enables of the memory system during an interleaved dram read access. use these to directly interface to either dram or transceiver output enable signals. leaf0# is asserted during an even leaf access. leaf1# is asserted during an odd leaf access.
80960vh 24 preliminary datasheet ma11:0 o r(x) h(q) p(q) multiplexed address signals are multi-purpose depending on the device that is selected. for memory banks 0 and 1, these signals output address bits a13:2. these address bits are incremented for each data transfer of a burst access. for dram bank, these signals output the row/column multiplexed address bits 11:0. the relationship between the ad31:0 lines and the ma11:0 lines depends on the bank size, type and arrangement of the dram that is accessed. mwe3:0# o r(1) h(q) p(q) memory write enable signals for write accesses to sram/flash devices. the mwes rising edge strobes valid data into these devices. mwe0# is asserted for writes to the be0# lane mwe1# is asserted for writes to the be1# lane mwe2# is asserted for writes to the be2# lane mwe3# is asserted for writes to the be3# lane ras3:0# o r(1) h(q) p(q) row address strobe signals are used for dram accesses and are asserted when the ma11:0 signals contain a valid row address. ras3:0# always deasserts after the last data transfer in a dram access. non-interleaved operation: ras0# = bank0 access ras1# = bank1 access ras2# = bank2 access ras3# = bank3 access interleaved operation: ras0,2# = even leaf ras1,3# = odd leaf table 8. memory controller signal descriptions (sheet 2 of 2) name type description table 9. dma, i 2 c units signal descriptions name type description dack# o r(h) h(q) p(q) dma demand mode acknowledge the dma controller asserts this signal to indicate (1) it can receive new data from an external device or (2) it has data to send to an external device. this signal has a weak internal pullup which is active during reset to ensure normal operation. dreq# i s(l) dma demand mode request external devices use this signal to indicate (1) new data is ready for transfer to the dma controller or (2) buffers are available to receive data from the dma controller. scl i/o od r(z) h(q) p(q) i 2 c clock provides synchronous i 2 c bus operation. sda i/o od r(z) h(q) p(q) i 2 c data used for data transfer and arbitration on the i 2 c bus. wait# o r(1) h(q) p(q) wait is an output that allows the dma controller to insert wait states during dma accesses to an external memory system.
80960vh preliminary datasheet 25 table 10. clock related signals name type description p_clk i synchronous pci bus clock provides the timing for all primary pci transactions and is the clock source for all internal units. all input/output timings are relative to p_clk . clkmode1:0# i clock mode are used to select the mode of operation in terms of the 80960 local bus / pci bus vs. the internal 80960 processor core. these signals are internally pulled high. this causes the 80960 processor core to run in dx mode after reset. in this mode, the 80960 processor core speed can be altered by using the core select register (csr). 00 - dx4 mode 01 - dx2 mode 10 - dx mode 11 - select speed via pci bus
80960vh 26 preliminary datasheet 3.1.2 324-lead pbga package figure 3. 324-plastic ball grid array top and side view a4628-01 pin #1 corner pin #1 i.d. d f e seating plate 30? e 1 d 1 a 2 a 1 a c top view side view note: all dimensions are in millimeters
80960vh preliminary datasheet 27 figure 4. 324-plastic ball grid array (top view) table 11. pbga 324 package dimensions pbga package dimensions min max n (# of balls) 324 a 2.14 2.52 a 1 0.50 0.70 a 2 1.12 1.22 d/e 26.80 27.20 d 1 /e 1 23.75 24.25 s 1 1.44 ref b 0.60 0.90 c 0.52 0.60 e1.27 a4630-01 b pin #1 corner 325 balls 20 x 20 matrix top view 1.0 3 places e s 1 e 2 1 4 3 6 5 8 79 11 10 13 12 15 14 17 16 18 20 a b c d e f g h j k l m n p r t u v w y 19
80960vh 28 preliminary datasheet table 12. 324-plastic ball grid array ballout in ball order (sheet 1 of 3) ball signal ball signal ball signal ball signal a1 v ss b12 p_lock# d3 clkmode1# e14 nc a2 wait# b13 v cc d4 v ss e15 nc a3 p_ad3 b14 p_c/be2# d5 p_ad2 e16 nc a4 v cc b15 v ss d6 v cc e17 nc a5 p_c/be0# b16 p_ad21 d7 p_ad7 e18 nc a6 v ss b17 v cc d8 v ss e19 nc a7 p_ad10 b18 p_ad24 d9 nc e20 p_ad31 a8 v cc b19 v ss d10 v cc f1 ma6 a9 p_ad13 b20 p_ad28 d11 v cc f2 v ss a10 p_ad14 c1 dp3 d12 v cc f3 ma11 a11 p_par c2 clkmode0 # d13 v ss f4 v cc a12 p_perr# c3 dack# d14 p_ad18 f5 nc a13 v cc c4 p_ad1 d15 v cc f6 v cc a14 p_trdy# c5 p_ad4 d16 p_ad26 f14 v cc a15 v ss c6 p_ad6 d17 v ss f15 v cc a16 p_ad17 c7 p_ad8 d18 p_ad30 f16 nc a17 p_ad22 c8 p_ad11 d19 v cc f17 v cc a18 p_idsel c9 nc d20 nc f18 p_req# a19 p_c/be3# c10 p_ad15 e1 ma9 f19 v ss a20 v ss c11 p_serr# e2 dp0 f20 p_gnt# b1 dreq# c12 p_devsel# e3 dp2 g1 nc b2 v ss c13 p_irdy# e4 v cc g2 ma5 b3 p_ad0 c14 p_ad16 e5 nc g3 ma7 b4 v cc c15 p_ad20 e6 nc g4 ma10 b5 p_ad5 c16 p_ad23 e7 nc g5 nc b6 v ss c17 p_ad25 e8 nc g6 v cc b7 p_ad9 c18 p_ad27 e9 nc g16 nc b8 v cc c19 p_ad29 e10 p_c/be1# g17 p_rst# b9 p_ad12 c20 v cc e11 p_stop# g18 p_intd# b10 v ss d1 dp1 e12 p_frame# g19 v cc
80960vh preliminary datasheet 29 b11 v ss d2 v cc e13 p_ad19 g20 vccpll2 h1 v cc k11 v ss m17 be3# r7 v cc h2 v cc k12 v ss m18 be2# r15 v cc h3 ma4 k16 be0# m19 be1# r16 nc h4 v ss k17 v cc m20 v cc r17 v cc h5 ma8 k18 dt/r# n1 v cc r18 ad23 h16 p_intc# k19 v ss n2 v cc r19 v ss h17 v ss k20 w/r# n3 mwe0# r20 v ss h18 p_intb# l1 leaf0# n4 v ss t1 cas4# h19 v cc l2 v ss n5 cas5# t2 cas1# h20 v cc l3 ce1# n16 nc t3 ras3# j1 ma0 l4 v cc n17 v ss t4 ras0# j2 ma1 l5 ce0# n18 ad30 t5 nc j3 ma2 l9 v ss n19 v cc t6 nc j4 ma3 l10 v ss n20 v cc t7 xint0# j5 v cc l11 v ss p1 cas7# t8 fail# j9 v ss l12 v ss p2 v cc t9 d/c#/ rst_mode# j10 v ss l16 ad31 p3 cas6# t10 rdyrcv# j11 v ss l17 v cc p4 cas3# t11 nc j12 v ss l18 ale p5 nc t12 v cc j16 ads# l19 v ss p15 v cc t13 ad6 j17 blast# l20 den# p16 nc t14 tck j18 sda m1 dwe1# p17 ad22 t15 tdi j19 scl m2 dwe0# p18 ad27 t16 nc j20 p_inta# m3 mwe3# p19 ad29 t17 ad17 k1 leaf1# m4 mwe2# p20 vcc5ref t18 ad20 k2 v ss m5 mwe1# r1 v ss t19 ad24 k3 dale0 m9 v ss r2 v ss t20 ad28 k4 v cc m10 v ss r3 cas2# u1 cas0# k5 dale1 m11 v ss r4 v cc u2 v cc k9 v ss m12 v ss r5 nc u3 ras1# ta ble 1 2. 324-plastic ball grid array ballout in ball order (sheet 2 of 3) ball signal ball signal ball signal ball signal
80960vh 30 preliminary datasheet k10 v ss m16 ad26 r6 v cc u4 v ss u5 v cc v13 ad5 y1 v ss u6 v cc v14 ad8 y2 xint5# u7 width/hltd0 v15 tms y3 xint3# u8 v ss v16 ad12 y4 xint1# u9 v cc v17 ad13 y5 v cc u10 v cc v18 ad16 y6 v ss u11 v cc v19 ad19 y7 lcdinit# u12 v cc v20 ad21 y8 hold u13 v ss w1 nc y9 lrdyrcv#/ stest u14 ad9 w2 v ss y10 vccpll1 u15 v cc w3 v cc y11 ad1 u16 v cc w4 v cc y12 ad4 u17 v ss w5 lrst# y13 ad7 u18 ad18 w6 v ss y14 trst# u19 v cc w7 v cc y15 v ss u20 ad25 w8 v cc y16 ad10 v1 ras2# w9 nmi# y17 nc v2 xint7# w10 v ss y18 ad14 v3 xint6# w11 v ss y19 ad15 v4 xint4# w12 ad3 y20 v ss v5 xint2# w13 v cc v6 width/hltd1/retry w14 v cc v7 nc w15 v ss v8 lock#/once# w16 nc v9 holda w17 ad11 v10 tdo w18 v cc v11 ad0 w19 v ss v12 ad2 w20 p_clk note: 1. do not connect any external logic to balls marked nc (no connect balls). table 12. 324-plastic ball grid array ballout in ball order (sheet 3 of 3) ball signal ball signal ball signal ball signal
80960vh preliminary datasheet 31 ta ble 1 3. 324-plastic ball grid array ballout in signal order (sheet 1 of 3) signal ball signal ball signal ball signal ball ad0 v11 ad31 l16 dwe0# m2 nc e6 ad1 y11 ads# j16 dwe1# m1 nc e7 ad2 v12 ale l18 fail# t8 nc e8 ad3 w12 be0# k16 hold y8 nc e9 ad4 y12 be1# m19 holda v9 nc e14 ad5 v13 be2# m18 lcdinit# y7 nc e15 ad6 t13 be3# m17 leaf0# l1 nc e16 ad7 y13 blast# j17 leaf1# k1 nc e17 ad8 v14 cas0# u1 lock#/once# v8 nc e18 ad9 u14 cas1# t2 lrdyrcv#/stest y9 nc e19 ad10 y16 cas2# r3 lrst# w5 nc f5 ad11 w17 cas3# p4 ma0 j1 nc f16 ad12 v16 cas4# t1 ma1 j2 nc g1 ad13 v17 cas5# n5 ma2 j3 nc g5 ad14 y18 cas6# p3 ma3 j4 nc g16 ad15 y19 cas7# p1 ma4 h3 nc n16 ad16 v18 ce0# l5 ma5 g2 nc p5 ad17 t17 ce1# l3 ma6 f1 nc p16 ad18 u18 clkmode0# c2 ma7 g3 nc r5 ad19 v19 clkmode1# d3 ma8 h5 nc r16 ad20 t18 d/c#/rst_mode# t9 ma9 e1 nc t5 ad21 v20 dack# c3 ma10 g4 nc t6 ad22 p17 dale0 k3 ma11 f3 nc t11 ad23 r18 dale1 k5 mwe0# n3 nc t16 ad24 t19 den# l20 mwe1# m5 nc v7 ad25 u20 dp0 e2 mwe2# m4 nc w1 ad26 m16 dp1 d1 mwe3# m3 nc w16 ad27 p18 dp2 e3 nc c9 nc y17 ad28 t20 dp3 c1 nc d9 nmi# w9 ad29 p19 dreq# b1 nc d20 p_ad0 b3 ad30 n18 dt/r# k18 nc e5 p_ad1 c4
80960vh 32 preliminary datasheet p_ad2 d5 p_c/be1# e10 tms v15 v cc n20 p_ad3 a3 p_c/be2# b14 trst# y14 v cc p15 p_ad4 c5 p_c/be3# a19 v cc a8 v cc r4 p_ad5 b5 p_clk w20 v cc a13 v cc r6 p_ad6 c6 p_devsel# c12 v cc b4 v cc r7 p_ad7 d7 p_frame# e12 v cc b8 v cc r15 p_ad8 c7 p_gnt# f20 v cc b13 v cc r17 p_ad9 b7 p_idsel a18 v cc b17 v cc u2 p_ad10 a7 p_inta# j20 v cc d2 v cc u6 p_ad11 c8 p_intb# h18 v cc d6 v cc u10 p_ad12 b9 p_intc# h16 v cc d10 v cc u11 p_ad13 a9 p_intd# g18 v cc d11 v cc u15 p_ad14 a10 p_irdy# c13 v cc d15 v cc u19 p_ad15 c10 p_lock# b12 v cc d19 v cc w4 p_ad16 c14 p_par a11 v cc f4 v cc w8 p_ad17 a16 p_perr# a12 v cc f6 v cc w13 p_ad18 d14 p_req# f18 v cc f14 v cc y5 p_ad19 e13 p_rst# g17 v cc f15 v cc a4 p_ad20 c15 p_serr# c11 v cc f17 v cc d12 p_ad21 b16 p_stop# e11 v cc g6 v cc g19 p_ad22 a17 p_trdy# a14 v cc h1 v cc j5 p_ad23 c16 ras0# t4 v cc h2 v cc m20 p_ad24 b18 ras1# u3 v cc h19 v cc p2 p_ad25 c17 ras2# v1 v cc h20 v cc u5 p_ad26 d16 ras3# t3 v cc k4 v cc u9 p_ad27 c18 rdyrcv# t10 v cc k17 v cc u12 p_ad28 b20 scl j19 v cc l4 v cc u16 p_ad29 c19 sda j18 v cc l17 v cc w3 p_ad30 d18 tck t14 v cc n1 v cc w7 p_ad31 e20 tdi t15 v cc n2 v cc w14 p_c/be0# a5 tdo v10 v cc n19 v cc w18 table 13. 324-plastic ball grid array ballout in signal order (sheet 2 of 3) signal ball signal ball signal ball signal ball
80960vh preliminary datasheet 33 v cc c20 v ss k2 v ss w10 v cc e4 v ss k9 v ss w11 v cc t12 v ss k10 v ss w15 vcc5ref p20 v ss k11 v ss w19 vccpll1 y10 v ss k12 v ss y1 vccpll2 g20 v ss k19 v ss y6 v ss a1 v ss l2 v ss y15 v ss a6 v ss l9 v ss y20 v ss a15 v ss l10 w/r# k20 v ss a20 v ss l11 wait# a2 v ss b2 v ss l12 width / hltd0 u7 v ss b6 v ss l19 width /hltd1/retry v6 v ss b10 v ss m9 xint0# t7 v ss b11 v ss m10 xint1# y4 v ss b15 v ss m11 xint2# v5 v ss b19 v ss m12 xint3# y3 v ss d4 v ss n4 xint4# v4 v ss d8 v ss n17 xint5# y2 v ss d13 v ss r1 xint6# v3 v ss d17 v ss r2 xint7# v2 v ss f2 v ss r19 v ss f19 v ss r20 v ss h4 v ss u4 v ss h17 v ss u8 v ss j9 v ss u13 v ss j10 v ss u17 v ss j11 v ss w2 v ss j12 v ss w6 note: 1. do not connect any external logic to balls marked nc (no connect balls). ta ble 1 3. 324-plastic ball grid array ballout in signal order (sheet 3 of 3) signal ball signal ball signal ball signal ball
80960vh 34 preliminary datasheet 3.2 package thermal specifications the device is specified for operation when t c (case temperature) is within the range of 0 c to 95 c. case temperature may be measured in any environment to determine whether the processor is within specified operating range. measure the case temperature at the center of the top surface, opposite the ballpad. 3.2.1 thermal specifications this section defines the terms used for thermal analysis. 3.2.1.1 ambient temperature ambient temperature, t a , is the temperature of the ambient air surrounding the package. in a system environment, ambient temperature is the temperature of the air upstream from the package. 3.2.1.2 case temperature to ensure functionality and reliability, the device is specified for proper operation when the case temperature, t c , is within the specified range in table 16, operating conditions (pg. 36) . when measuring case temperature, attention to detail is required to ensure accuracy. if a thermocouple is used, then calibrate it before taking measurements. errors may result when the measured surface temperature is affected by the surrounding ambient air temperature. such errors may be due to a poor thermal contact between thermocouple junction and the surface, heat loss by radiation, or conduction through thermocouple leads. to minimize measurement errors: ? use a 35 gauge k-type thermocouple or equivalent. ? attach the thermocouple bead or junction to the package top surface at a location corresponding to the center of the die (). the center of the die gives a more accurate measurement and less variation as the boundary condition changes. ? attach the thermocouple bead or junction at a 90 angle by an adhesive bond (such as thermal epoxy or heat-tolerant tape) to the package top surface as shown in . figure 5. thermocouple attachment thermocouple bead thermocouple wire epoxy fillet
80960vh preliminary datasheet 35 3.2.1.3 thermal resistance the thermal resistance value for the case-to-ambient, q ca , is used as a measure of the cooling solutions thermal performance. 3.2.2 thermal analysis table 14 lists the case-to-ambient thermal resistances of the 80960vh for different air flow rates without a heat sink. to calculate t a , the maximum ambient temperature to conform to a particular case temperature: t a = t c - p ( q ca ) compute p by multiplying i cc and v cc . values for q jc and q ca are given in table 14 . junction temperature (t j ) is commonly used in reliability calculations. t j can be calculated from q jc (thermal resistance from junction to case) using the following equation: t j = t c + p ( q jc ) similarly, when t a is known, the corresponding case temperature (t c ) can be calculated as follows: t c = t a + p ( q ca ) the q ja (junction-to-ambient) for this package is currently estimated at 26.54 c/watt with no airflow. q ja = q jc + q ca table 14. 324-lead pbga package thermal characteristics thermal resistance c/watt parameter airflow ft./min (m/sec) 0 (0) 100 (0.50) 200 (1.01) 400 (2.03) 600 (3.04) 800 (4.06) q jc (junction-to-case) 1.36 1.36 1.36 1.36 1.36 1.36 q ca (case-to-ambient) without heatsink 25.18 20.30 18.29 16.57 15.55 14.75 note: 1. this table applies to a pbga device soldered directly onto a board. q ja q jc q ca
80960vh 36 preliminary datasheet 4.0 electrical specifications 4.1 v cc5 pin requirements (v diff ) in mixed voltage systems that drive 80960vh inputs in excess of 3.3 v, the v cc5 pin must be connected to the systems 5 v supply. to limit current flow into the v cc5 pin, there is a limit to the voltage differential between the v cc5 pin and the other v cc pins. the voltage differential between the 80960vh v cc5 pin and its 3.3 v v cc pins should never exceed 2.25 v. this limit applies to power-up, power-down, and steady-state operation. table 17 outlines this requirement. meeting this requirement ensures proper operation and guarantees that the current draw into the v cc5 pin does not exceed the i cc5 specification. if the voltage difference requirements cannot be met due to system design limitations, then an alternate solution may be employed. as shown in figure 6., a minimum of 100 w series resistor may be used to limit the current into the v cc5 pin. this resistor ensures that current drawn by the v cc5 pin does not exceed the maximum rating for this pin. table 15. absolute maximum ratings parameter maximum rating storage temperature C55 c to + 125 c case temperature under bias 0 c to + 95 c supply voltage wrt. v ss C0.5 v to + 4.6 v supply voltage wrt. v ss on v cc5 C0.5 v to + 6.5 v voltage on any ball wrt. v ss C0.5 v to v cc + 0.5 v notice : this data sheet contains information on products in the design phases of development. the specifications are subject to change without notice. contact your local intel representative before finalizing a design. warning: stressing the device beyond the absolute maximum ratings may cause permanent damage. these are stress ratings only. operation beyond the operating conditions is not recommended and extended exposure beyond the operating conditions may affect device reliability. table 16. operating conditions symbol parameter min max units notes v cc supply voltage 3.0 3.6 v (1) v cc5 input protection bias 3.0 5.25 v (1) f p_clk input clock frequency 16 33.33 mhz t c case temperature under bias i960 ? vh processor (324 pbga) 0 95 c note: 1. the 80960vh processor is produced on intels advanced cmos process. proper bulk decoupling must be used to prevent device damage during power up and power down. power supply behavior during these transitions, without proper bulk decoupling, can cause the power supply to exceed the maximum v cc specification, causing device damage.
80960vh preliminary datasheet 37 this resistor is not necessary in systems that can guarantee the v diff specification. in 3.3 v-only systems and systems that drive 80960vh pins from 3.3 v logic, connect the v cc5 pin directly to the 3.3 v v cc plane. 4.2 v ccpll pin requirements to reduce clock skew on the i960 jx processor, the v ccpll pin for the phase lock loop (pll) circuit is isolated on the pinout. the lowpass filter, as shown in figure 7., reduces noise-induced clock jitter and its effects on timing relationships in system designs. the 4.7 f capacitor must be (low esr solid tantalum), the 0.01 f capacitor must be of the type x7r and the node connecting v ccpll must be as short as possible. figure 6. v cc5 current-limiting resistor +5 v (0.25 v) v cc5 pin 100 w (5%, 0.5 w) ta ble 1 7. v diff specification for dual power supply requirements (3.3 v, 5 v) symbol parameter min max units notes v diff v cc5 -v cc difference 2.25 v v cc5 input should not exceed v cc by more than 2.25 v during power-up and power-down, or during steady-state operation. figure 7. v ccpll lowpass filter 10 w , 5%, 1/8w v cc (board plane) v ccpll (on i960 ? jx processors) f_ca078a 0.01f 4.7f +
80960vh 38 preliminary datasheet 4.3 dc specifications table 18. dc characteristics symbol parameter min max units notes v il input low voltage -0.5 0.8 v (1) v ih1 input high voltage for all signals except p_clk 2.0 v cc + 0.5 v(1) v ol1 output low voltage processor signals 0.45 v i ol = 6 ma (3) v oh1 output high voltage processor signals 2.4 v cc - 0.5 v i oh = -2 ma (3) i oh = -200 m a (3) v ol2 output low voltage pci signals 0.55 v i ol = 1.5 ma (1) v oh2 output high voltage pci signals 2.4 v i oh = 0.5 ma (1) v ol3 output low voltage memory controller normal drive 0.45 v i ol = 6 ma (4) v oh3 output high voltage memory controller normal drive 2.4 v i oh = -2 ma (4) v ol4 output low voltage memory controller high drive 0.45 v i ol = 7 ma v oh4 output high voltage memory controller high drive 2.4 v i oh = -2 ma c in input capacitance - pbga 10 pf f p_clk = t f min (1, 2) c out i/o or output capacitance - pbga 10 pf f p_clk = t f min (1, 2) c clk p_clk capacitance - pbga 5 12 pf f p_clk = t f min (1, 2) c idsel idsel ball capacitance 8 pf (1) l pin ball inductance 20 nh (1) notes: 1. as required by the pci local bus specification , revision 2.2. 2. not tested. 3. processor signals include ad31:0, ale, ads#, be3:0#, width/hltd0, width/hltd1/retry, d/c#/rst_mode#, w/ r#, dt/r#, den#, blast#, lrdyrcv#, lock#/once#, hold, fail#, tdo, dack#, wait#, sda, scl. 4. memory controller signals include ma11:0, dp3:0, ras3:0#, cas7:0#, mwe3:0#, dwe1:0#, dale1:0, ce1:0#, leaf1:0#. 5. memory controller signals capable of high drive are ma11:0, cas7:0#, ras3:0#, dwe1:0#.
80960vh preliminary datasheet 39 ta ble 1 9. i cc characteristics symbol parameter typ max units notes i li1 input leakage current for each signal except pci bus signals, lock#/once#, width/ hltd0, width/hltd1/retry, blast#, d/c#/rst_mode#, den#, tms, trst#, tdi, dack#/pllen, lcdinit#, lrdyrcv#/stest, clkmode1:0# 5 m a v in = 0.8 v (v il ) and 2.0 v (v ih ) i li2 input leakage current for lock#/once#, width/hltd0, width/hltd1/retry, blast#, d/c#/rst_mode#, den#, tms, trst#, tdi, dack#/pllen, lcdinit#, lrdyrcv#/stest, clkmode1:0# -140 -250 m av in = 0.45 v (1) i li3 input leakage current for pci bus signals (except pclk) 5 m a v in = 0.8 v (v il ) and 2.0 v (v ih ) i lo output leakage current 5 m a0.4 v out v cc i cc active (power supply) power supply current i960 ? vh processor dx mode 450 ma (1,2) dx2 mode 590 ma (1,2) dx4 mode 720 ma (1,2) i cc active (thermal) thermal current i960 ? vh processor dx mode 390 ma (1,3) dx2 mode 550 ma (1,3) dx4 mode 690 ma (1,3) i cc active (power modes) reset mode i960 ? vh processor once mode i960 ? vh processor 470 40 ma (4) (4) notes: 1. measured with device operating and outputs loaded to the test condition in figure 8. 2. i cc active (power supply) value is provided for selecting your systems power supply. it is measured using one of the worst case instruction mixes with v cc = 3.6 v and ambient temperature = 55 c. this parameter is characterized but not tested. 3. i cc active (thermal) value is provided for your systems thermal management. typical i cc is measured with v cc = 3.3 v and ambient temperature = 55 c. this parameter is characterized but not tested. 4. i cc active (power modes) refers to the i cc values that are tested when the device is in reset mode or once mode with v cc = 3.6 v and ambient temperature = 55 c.
80960vh 40 preliminary datasheet 4.4 ac specifications table 20. input clock timings symbol parameter min max units notes t f p_clk frequency 16 33.33 mhz t c p_clk period 30 62.5 ns (1) t cs p_clk period stability 250 ps adjacent clocks (2,3) t ch p_clk high time 12 ns measured at 1.5 v (2,3) t cl p_clk low time 12 ns measured at 1.5 v (2,3) t cr p_clk rise time 4 v/ns 0.4 v to 2.4 v (2,3) t cf p_clk fall time 4 v/ns 2.4 v to 0.4 v (2,3) notes: 1. see figure 9, (pg. 46). 2. to ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter frequency spectrum should not have any power peaking between 500 khz and 1/3 of the p_clk frequency. 3. not tested. table 21. synchronous output timings symbol parameter min max units notes t ov1 output valid delay - all local bus signals except ale inactive and dt/r# 2 15.5 ns (1,2,5) t ov2 output valid delay, dt/r# 0.5 t c +3 0.5 t c +15 ns (2,5) t ov3 output valid delay - pci signals except p_req# 2 11 ns (2,5) t ov4 output valid delay p_req# 2 12 ns (2,5) t ov5 output valid delay - dp3:0 3 19 ns (2,5) t of output float delay 3 13 ns (3,4,5) notes: 1. inactive ale refers to the falling edge of ale. for inactive ale timings, see table 23, relative output timings (pg. 42) . 2. see figure 10, (pg. 46). 3. a float condition occurs when the output current becomes less than i lo . float delay is not tested, but is designed to be no longer than the valid delay. 4. see figure 11, (pg. 47). 5. outputs precharged to v cc5 maximum.
80960vh preliminary datasheet 41 table 22. synchronous input timings sym parameter min max units notes t is1 input setup to p_clk nmi#, xint7:0#, dp3:0 6 ns (1,2) t is1a input setup to p_clk for all accesses except expansion rom accesses ad31:0 only 6 ns (1,2) t is1b input setup to p_clk during expansion rom accesses ad31:0 only 8 ns (1,2) t ih1 input hold from p_clk ad31:0, nmi#, xint7:0#, dp3:0 2 ns (1,2,4) t is2 input setup to p_clk rdyrcv# and hold 10 ns (2) t ih2 input hold from p_clk rdyrcv# and hold 2 ns (2) t is3 input setup to p_clk lock#/once#, stest 7 ns (1,2,4) t ih3 input hold from p_clk lock#/once#, stest 3 ns (1,2,4) t is4 input setup to p_clk dreq# 12 ns (2) t ih4 input hold from p_clk dreq# 7 ns (2) t is5 input setup to p_clk pci signals except p_gnt# 7 ns (2) t ih5 input hold from p_clk pci signals 0 ns (2,4) t is6 input setup to p_clk p_rst# - dx4 mode 6 ns (2,3) t is6 input setup to p_clk p_rst# - dx2 and dx mode 10 ns (2,3) t ih6 input hold to p_clk p_rst# 2 ns (2,3,4) t is7 input setup to p_clk p_gnt# 10 ns (2) t is8 input setup to p_rst# width/hltd0, width/hltd1/retry, d/c#/rst_mode# 7 ns (1,2,4) t ih8 input hold from p_rst# width/hltd0, width/hltd1/retry, d/c#/rst_mode# 3 ns (1,2,4) notes: 1. setup and hold times must be met for proper processor operation. nmi#, and xint7:0# may be synchronous or asynchro- nous. meeting setup and hold time guarantees recognition at a particular clock edge. for asynchronous operation, nmi#, and xint7:0# must be asserted for a minimum of two p_clk periods to guarantee recognition. 2. see figure 12, (pg. 47). 3. p_rst# may be synchronous or asynchronous. meeting setup and hold time guarantees recognition at a particular clock edge. 4. guaranteed by design. may not be 100% tested.
80960vh 42 preliminary datasheet 4.4.1 relative output timings 4.4.2 memory controller relative output timings table 23. relative output timings symbol parameter min max units notes t lxl ale width 0.5t c -3 ns (1,2,4) t lxa address hold from ale inactive 0.5t c -1 ns equal loading (1,2,4) t dxd dt/r# valid to den# active 0.5t c -3 ns equal loading (1,3,4) notes: 1. guaranteed by design. may not be 100% tested. 2. see figure 13, (pg. 47). 3. see figure 14, (pg. 48) 4. outputs precharged to v cc5 maximum. table 24. fast page mode non-interleaved dram output timings symbol description min max units notes t ov6 ras3:0# rising and falling edge output valid delay 19ns2 t ov7 cas7:0# rising edge output valid delay 1 8 ns 2 t ov8 cas7:0# falling edge output valid delay 0.5tc+1 0.5tc+8 ns 1,2 t ov9 ma11:0 output valid delay-row address 0.5tc+1 0.5tc+10 ns 1,2 t ov10 ma11:0 output valid delay-column address 1 10 ns 2 t ov11 dwe1:0# rising and falling edge output valid delay 111ns2 notes: 1. signal generated on the rising edge of an internally generated 2xclk which corresponds to the center of an p_clk period. for testing purposes, the signal is specified relative to the rising edge of p_clk with the 0.5tc period offset. 2. output switching between v cc3 maximum and v ss . table 25. fast page mode interleaved dram output timings (sheet 1 of 2) symbol description min max units notes t ov12 ras3:0# rising and falling edge output valid delay 19ns2 t ov13 cas7:0# rising edge output valid delay 1 8 ns 2 t ov14 cas7:0# falling edge output valid delay 0.5tc+1 0.5tc+8 ns 1,2 t ov15 ma11:0 output valid delay-row address 0.5tc+1 0.5tc+10 ns 1,2 t ov16 ma11:0 output valid delay-column address 1 10 ns 2 t ov17 dwe1:0# rising and falling edge output valid delay 111ns2 notes: 1. signal generated on the rising edge of an internally generated 2xclk which corresponds to the center of an p_clk period. for testing purposes, the signal is specified relative to the rising edge of p_clk with the 0.5tc period offset. 2. output switching between v cc3 maximum and v ss .
80960vh preliminary datasheet 43 t ov18 dale1:0 initial falling edge output valid delay 1 10 ns 2 t ov19 dale1:0 burst falling edge output valid delay 0.5tc+1 0.5tc+10 ns 1,2 t ov20 dale1:0 rising edge output valid delay 1 10 ns 2 t ov21 leaf1:0# rising and falling edge output valid delay 110ns2 table 25. fast page mode interleaved dram output timings (sheet 2 of 2) symbol description min max units notes notes: 1. signal generated on the rising edge of an internally generated 2xclk which corresponds to the center of an p_clk period. for testing purposes, the signal is specified relative to the rising edge of p_clk with the 0.5tc period offset. 2. output switching between v cc3 maximum and v ss . table 26. edo dram output timings symbol description min max units note s t ov22 ras3:0# rising and falling edge output valid delay 1 9 ns 2 t ov23 cas7:0# rising edge output valid delay - read cycles 0.5tc+1 0.5tc+8 ns 1,2 t ov24 cas7:0# falling edge output valid delay - read cycles 18ns2 t ov25 cas7:0# rising edge output valid delay - write cycles 18ns2 t ov26 cas7:0# falling edge output valid delay - write cycles 0.5tc+1 0.5tc+8 ns 1,2 t ov27 ma11:0 output valid delay - row address 0.5tc+1 0.5tc+10 ns 1,2 t ov28 ma11:0 output valid delay - column address read cycles 0.5tc+1 0.5tc+10 ns 1,2 t ov29 ma11:0 output valid delay - column address write cycles 1 10 ns 2 t ov30 dwe1:0# rising and falling edge output valid delay 1 11 ns 2 notes: 1. signal generated on the rising edge of an internally generated 2xclk which corresponds to the center of an p_clk period. for testing purposes, the signal is specified relative to the rising edge of p_clk with the 0.5tc period offset. 2. output switching between v cc3 maximum and v ss . table 27. sram/rom output timings (sheet 1 of 2) symbol description min max units notes t ov40 ce1:0# rising and falling edge output valid delay 18ns2 t ov41 mwe3:0# rising edge output valid delay 1 9 ns 2 t ov42 mwe3:0# falling edge output valid delay 0.5tc+1 0.5tc +9 ns 1,2
80960vh 44 preliminary datasheet 4.4.3 boundary scan test signal timings t ov43 ma11:0 output valid delay - initial address 0.5tc+1 0.5tc +10 ns 2 t ov44 ma11:0 output valid delay - burst address 1 10 ns 2 notes: 1. signal generated on the rising edge of an internally generated 2xclk which corresponds to the center of an p_clk period. for testing purposes, the signal is specified relative to the rising edge of p_clk with the 0.5tc period offset. 2. output switching between v cc3 maximum and v ss . table 27. sram/rom output timings (sheet 2 of 2) symbol description min max units notes table 28. boundary scan test signal timings symbol parameter min max units notes t bsf tck frequency 0 0.5t f mhz t bsch tck high time 15 ns measured at 1.5 v (1) t bscl tck low time 15 ns measured at 1.5 v (1) t bscr tck rise time 5 ns 0.8 v to 2.0 v (1) t bscf tck fall time 5 ns 2.0 v to 0.8 v (1) t bsis1 input setup to tck tdi, tms 4 ns t bsih1 input hold from tck tdi, tms 6ns(1) t bsov1 tdo valid delay 3 30 ns relative to falling edge of tck (1,2) t bsof1 tdo float delay 3 30 ns relative to falling edge of tck (1,2) t bsov2 all outputs (non-test) valid delay 3 30 ns relative to falling edge of tck (1,2) t bsof2 all outputs (non-test) float delay 3 30 ns relative to falling edge of tck (1,2) t bsis2 input setup to tck all inputs (non-test) 4ns(1) t bsih2 input hold from tck all inputs (non-test) 6ns(1) notes: 1. guaranteed by design. not tested. 2. outputs precharged to v cc5 maximum.
80960vh preliminary datasheet 45 4.4.4 i 2 c interface signal timings 4.5 ac test conditions the ac specifications in section 4.4, ac specifications (pg. 40) are tested with the 50 pf load indicated in . ta ble 2 9. i 2 c interface signal timings symbol parameter std. mode fast mode units notes min max min max f scl scl clock frequency 0 100 0 400 khz t buf bus free time between stop and start condition 4.7 1.3 m s(1) t hdsta hold time (repeated) start condition 4 0.6 m s (1,3) t low scl clock low time 4.7 1.3 m s (1,2) t high scl clock high time 4 0.6 m s (1,2) t susta setup time for a repeated start condition 4.7 0.6 m s(1) t hddat data hold time 0 0 0.9 m s(1) t sudat data setup time 250 100 ns (1) t r scl and sda rise time 1000 20+0.1c b 300 ns (1,4) t f scl and sda fall time 300 20+0.1c b 300 ns (1,4) t susto setup time for stop condition 4 0.6 m s(1) notes: 1. see figure 15, (pg. 48). 2. not tested. 3. after this period, the first clock pulse is generated. 4. c b = the total capacitance of one bus line, in pf. figure 8. ac test load output ball c l = 50 pf for all signals c l
80960vh 46 preliminary datasheet 4.6 ac timing waveforms figure 9. p_clk, tclk waveform 2.0v 1.5v 0.8v t cf t ch t cl t c t cr figure 10. t ov output delay waveform p_clk 1.5v 1.5v t ovx max t ovx min 1.5v 1.5v valid
80960vh preliminary datasheet 47 figure 11. t of output float waveform figure 12. t is and t ih input setup and hold waveform figure 13. t lxl and t lxa relative timings waveform 1.5v 1.5v t of p_clk p_clk valid 1.5v 1.5v 1.5v t isx t ihx 1.5v p_clk ale 1.5v 1.5v 1.5v 1.5v 1.5v ad31:0 valid t lxa t a t w /t d 1.5v val id 1.5v t lxl
80960vh 48 preliminary datasheet figure 14. dt/r# and den# timings waveform figure 15. i 2 c interface signal timings p_clk dt/r# 1.5v 1.5v 1.5v den# va li d t dxd t a t w /t d t ovx t ovx sda scl t buf stop start t low t hdsta t high t r t hddat t f t sudat t susta repeated t hdsta t sp stop t susto start
80960vh preliminary datasheet 49 4.7 memory controller output timing waveforms figure 16. fast page-mode read access, non-interleaved, 2,1,1,1 wait state, 32-bit 80960 local bus addr data p_clk ad31:0 t a t w t w t d t w t d t w t d t w t d in ma11:0 ale ads# w/r# blast# dt/r# den# dwe0# ras0# cas3:0# lrdyrcv# data in data in data in col col col col row t r rdyrcv#
80960vh 50 preliminary datasheet figure 17. fast page-mode write access, non-interleaved, 2,1,1,1 wait states, 32-bit 80960 local bus data data data p_clk ad31:0 t a t w t w t d t w t d t w t d t w t d t r out out out ma11:0 ale ads# be3:0# w/r# blast# dt/r# mwe0# dwe0# ras0# cas3:0# addr row col col col col lrdyrcv# rdyrcv# datao ut
80960vh preliminary datasheet 51 figure 18. fpm dram system read access, interleaved, 2,0,0,0 wait states p_clk ras[n]# ma[11:0] ad[31:0] t a t w t w t d t d t d t d col row dwe[1:0]# ras[n+1#] dale[0]# cas[3:0]# dale[1]# cas[7:4]# d in d in d in d in leaf[0]# leaf[1]# col t r addr
80960vh 52 preliminary datasheet figure 19. fpm dram system write access, interleaved, 1,0,0,0 wait states p_clk ras[n]# ma[11:0] ad[31:0] t a t w t d t d t d t d t r col row dwe[1:0]# dale[0]# cas[3:0]# dale[1]# cas[7:4]# leaf[0]# leaf[1]# addr data out data out data out t r col ras[n+1]# data out
80960vh preliminary datasheet 53 figure 20. edo dram, read cycle p_clk ras# ma[11:0] ad[31:0] t a t w t w t d t d t d t d t r col col col col row cas# d addr in d in d in d in figure 21. edo dram, write cycle t a t w t d t d t d t d t r col col col col row d p_clk ras# ma[11:0] ad[31:0] cas# addr out d out d out d out
80960vh 54 preliminary datasheet figure 22. 32-bit bus, sram read accesses with 0 wait states t a t d t d t d t d t r addr addr addr addr p_clk ce[1]# ma[11:0] ad[31:0] mwe[3:0]# addr d in d in d in d in figure 23. 32-bit bus, sram write accesses with 0 wait states t a t d t d t d t d t r addr addr addr addr p_clk ce[1]# ma[11:0] ad[31:0] mwe[3:0]# addr d out d out d out d out
80960vh preliminary datasheet 55 5.0 bus functional waveforms figure 24. non-burst read and write transactions without wait states, 32-bit 80960 local bus p_clk ad31:0 ale ads# be3:0# width1:0 d/c# w/r# dt/r# den# lrdyrcv# blast# addr d in invalid 10 10 t a t d t r t i t i t a t d t r t i t i rdyrcv# addr data out d in
80960vh 56 preliminary datasheet figure 25. burst read and write transactions without wait states, 32-bit 80960 local bus addr d d addr data data data 1 0 1 0 p_clk ad31:0 ale ads# be3:0# width1:0 d/c# w/r# blast# dt/r# den# t a t d t d t r t a t d t d t d t d t r in in out out out lrdyrcv# rdyrcv# data out
80960vh preliminary datasheet 57 figure 26. burst write transactions with 2,1,1,1 wait states, 32-bit 80960 local bus addr data 1 0 data data data p_clk ad31:0 ale ads# be3:0# width1:0 d/c# w/r# blast# dt/r# den# t a t w t w t d t w t d t w t d t w t d t r out out out out lrdyrcv# rdyrcv#
80960vh 58 preliminary datasheet figure 27. burst read and write transactions without wait states, 8-bit 80960 local bus addr d d addr data data data data p_clk ad31:0 ale ads# be1/a1# width1:0 d/c# w/r# blast# dt/r# den# t a t d t d t r t a t d t d t d t d t r 00 01 10 11 00 00 be0/a0# in in out out out out 00 or 10 01 or 11 lrdyrcv# rdyrcv#
80960vh preliminary datasheet 59 figure 28. burst read and write transactions with 1, 0 wait states and extra tr state on read, 16-bit 80960 local bus addr d d addr data p_clk ad31:0 ale ads# be3# width1:0 d/c# w/r# blast# dt/r# den# t w t d t d t r t r t a t w t d t d t r t a be0# be1/a1# 01 01 0 1 01 out in in lrdyrcv# rdyrcv# data out
80960vh 60 preliminary datasheet figure 29. bus transactions generated by double word read bus request, misaligned one byte from quad word boundary, 32-bit 80960 local bus t a t d t r t a t d t r t a t d t r t a t d t r p_clk ad31:0 ale ads# be3:0# width1:0 d/c# w/r# blast# dt/r# den# 1 1 0 1 0 0 1 1 0 0 0 0 1 1 1 0 1 0 val id aa a d a d in in d in d in lrdyrcv# rdyrcv#
80960vh preliminary datasheet 61 figure 30. hold/holda waveform for bus arbitration p_clk val id outputs: ad31:0, ale, ads#, be3:0# d/c#/rstmode# lrdyrcv#, fail# width/hltd1, width/hltd1/retry, w/r#, dt/r#, den#, blast#, lock#/once# hold holda ~ ~ ~ ~ ~ ~ ~ ~ (note) note: hold is sampled on the rising edge of p_clk. holda is granted after the latency counter in the local bus arbiter expires. the processor asserts holda to grant the bus on the same edge in which it recognizes val id ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t i or t r t h t h t i or t a hold if the last state was t i or the last t r of a bus transaction. similarly, the processor deasserts holda on the same edge in which it recognizes the deassertion of hold.
80960vh 62 preliminary datasheet figure 31. 80960 core cold reset waveform p_clk ads#, be3:0# ale, dt/r#, p_rst# lock#/ stest v cc hold, holda, w/r# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ first bus activity ~ ~ ~ ~ ~ ~ valid ~ ~ (output) once# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ d/c#/rst_mode#, ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ blast#, den# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ v 100 s for pll stabilization. cc and p_clk stable to p_rst# high, minimum ~ ~ built-in self test approxi- mately 414,000 p_clk periods (if selected) (input) ~ ~ lrdyrcv valid 1. the processor asserts fail# during built-in self-test. if self- test passes, the fail# is deasserted.the processor also asse rts fail# during the bus confidence test. if the bus confidence test passes, fail# is deasserted and the processor begins user program ex ecution. notes: 2. if the processor fails built-in self-test, it initiates one dummy load bus access. the load address indicates the point of self-test failure. width/hltd0, width/hltd1/retry 1 ms power and clock stable ~ ~ ad31:0 ~ ~ ~ ~ idle (note 2) ~ ~ ~ ~ ~ ~ fail# ~ ~ ~ ~ ~ ~ ~ ~ (note 1) ~ ~ ~ ~ ~ ~ ~ ~
80960vh preliminary datasheet 63 figure 32. 80960 local bus warm reset waveform ~ ~ maximum l_rst# low to reset state 4 p_clk cycles ~ ~ ~ ~ ~ ~ p_clk ad31:0 stest l_rst# l_rst# high to first bus minimum l_rst# low time 16 p_clk cycles ~ ~ ~ ~ ~ ~ ~ ~ holda ~ ~ ~ ~ ~ ~ ~ ~ va l id ale, w/r#,dt/r# ads#, be3:0#,den#, blast#, ~ ~ ~ ~ fail# ~ ~ ~ ~ hold ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ lock#/once# ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ activity, 46 p_clk cycles ~ ~ ~ ~ ~ ~ ~ ~ d/c#/rst_mode#, width/hltd0, width/hltd1/retry,lrdyrcv# ~ ~ p_rst# ~ ~ ~ ~ note: local bus warm reset occurs when bit 5 in the reset/retry control register (rrcr) is set; l_rst# asserts when all atu and/or dma activity ceases on the pci buses. l_rst# asserts in a minimum of 18 clock cycles after rrcr bit 5 is set. ~ ~
80960vh 64 preliminary datasheet 6.0 device identification on reset during the manufacturing process, values characterizing the i960 ? vh processor type and stepping are programmed into the memory-mapped registers. the 80960vh contains two read-only device id mmrs. one holds the processor device id (pdidr - 0000 1710h) and the other holds the i960 core processor device id (deviceid - ff00 8710h). during initialization, the pdidr is placed in g0. the device identification values are compliant with the ieee 1149.1 specification and intel standards. table 30 describes the fields of the two device ids. note: values programmed into this register vary with stepping. refer to the i960 ? vh processor specification update (273174-001) for the correct value. table 30. processor device id register - pdidr lba: pci: 1710h na legend: na = not accessiblero = read only rv = reservedpr = preservedrw = read/write rs = read/setrc = read clear lba = 80960 local bus address pci = pci configuration address offset bit default description 31:28 x version - indicates stepping changes. 27 x v cc - indicates device voltage type. 0=5.0v 1=3.3v 26:21 x product type - indicates the generation or family member. 20:17 x generation type - indicates the generation of the device. 16:12 x model type - indicates member within a series and specific model information. 11:01 x manufacturer id - indicates manufacturer id assigned by ieee. 0000 0001 001 = intel corporation 0xconstant pci lba 28 24 20 16 12 8 4 0 31 ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na ro na

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